| Semiconductor |
|
As both fab-less and fabs vie for supremacy in their chosen niche markets, be it GPS, wireless applications or power distribution, the need for smaller component packages (silicon) becomes central to success or failure. As the adoption of micro ball grid arrays (BGAs) becomes more widespread, the ability to test silicon becomes increasingly difficult. Clearly, specialist boards need to be developed as part of a package that the major chip manufacturers (STMicro, Texas Instruments, Intel etc) can sell to global OEMs in such markets as mobile telecoms, consumer electronics and RF communications. Exceptions ability in the manufacture of reliable test boards (or reference designs) to accompany the initial supply of prototype packaged silicon is a key element of the bigger picture. Without the promise of the improved silicon and the board to analyse and test its performance, the chip will never go on to large scale production, where the real profits are recouped when their production runs rise to tens of thousands, not a handful. To improve the efficiency and fan out of micro BGAs within the board – be it an IC Substrate, Reference Design or DUT (device under test - Load/Probe test board) - we are increasingly seeing the adoption of more layers within the PCB design. This can include increasing the number of layers from six to twelve or even sixteen to accommodate high speed data transfer and the sheer volume of I/O needed to be handled by the dictation of multiple micro BGAs within a single platform PCB. |